1. Field of the Invention
The present invention generally relates to semiconductor devices, and, more particularly, to a semiconductor device having a multilayer interconnection structure.
2. Description of the Related Art
The number of active elements in recent ultra-fine semiconductor integrated circuits have greatly increased. To interconnect those numerous active elements, a first wiring layer is covered with an interlayer insulating film, and a second wiring layer is formed on the interlayer insulating film. A conductive plug is then formed in the interlayer insulating film so as to connect the first and second wiring layers. This structure is called a multilayer interconnection structure.
FIG. 1 shows the structure of a conventional semiconductor device 10 having a multilayer interconnection structure.
As shown in FIG. 1, the semiconductor device 10 is formed on a Si substrate 11 provided with isolation areas 11A and 11B. The isolation areas 11A and 11B define an active region on the Si substrate 11, and diffusion areas 11a and 11b acting as source and drain of a MOS transistor are formed in the active region.
On the Si substrate 11, a gate insulating film 12a is formed to cover a channel region formed between the diffusion areas 11a and 11b, and a gate electrode 12b is formed on the gate insulating film 12a. In FIG. 1, sidewall insulating films 12c and 12d are further formed on both side surfaces of the gate electrode 12b. The gate insulating film 12a, the gate electrode 12b, and the sidewall insulating films 12c and 12d constitute a gate structure of the MOS transistor. In the figure, the gate electrode 12b has a polycide structure, having a silicide layer formed on a polysilicon pattern, as indicated by a dotted area in the figure.
On the Si substrate 11, a first interlayer insulating film 13 is formed to cover the gate electrode 12b and the sidewall insulating films 12c and 12d. In the first interlayer insulating film 13, contact holes 13a and 13b are formed to expose the diffusion areas 11a and 11b. 
A first-layer wiring pattern 14a to be electrically in contact with the diffusion area 11a through the contact hole 13a is formed on the first interlayer insulting film 13. Another first-layer wiring pattern 14b to be electrically in contact with the diffusion area 11b through the contact hole 13b is also formed on the first interlayer insulating film 13. Here, a conductive plug 14p extends from the wiring pattern 14a through the contact hole 13a, while a conductive plug 14q extends from the wiring pattern 14b through the contact hole 13b. The wiring pattern 14b may be a contact pad to make electric contact with the diffusion area 11b. 
On the first interlayer insulating film 13, a second interlayer insulating film 15 is formed to cover the wiring patterns 14a and 14b. In the second interlayer insulating film 15, a contact hole 15a that penetrates through the first interlayer insulating film 13 is formed to expose the gate electrode 12b. 
On the second interlayer insulating film 15, a second-layer wiring pattern 16 is formed to make electric contact with the gate electrode 12b through the contact hole 15a. A third interlayer insulating film 17 to cover the wiring pattern 16 is further formed on the second interlayer insulating film 15. Here, a conductive plug 16p extends from the wiring pattern 16 through the contact hole 15a. In the third interlayer insulating film 17, contact holes 17a and 17b are formed to expose the wiring patterns 14a and 14b, respectively. The wiring pattern 16 may be a contact pad to make electric contact with the gate electrode 12b. 
On the third interlayer insulating film 17, third-layer wiring patterns 18a and 18b are formed to make contact with the wiring pattern 14a through the contact hole 17a and with the wiring pattern 14b through the contact hole 17b, respectively. On the third interlayer insulating film 17, a fourth interlayer insulating film 19 is further formed to cover the wiring patterns 18a and 18b. Here, a conductive plug 18p extends from the wiring pattern 18a through the contact hole 17a, and a conductive plug 18q extends from the wiring pattern 18b through the contact hole 17b. 
In the fourth interlayer insulating film 19, a contact hole 19a is formed to expose the wiring pattern 16. The contact hole 19a is covered with a conductive plug 20 to make electric contact with the wiring pattern 16.
With the above structure, the wiring pattern can be simplified, compared with the wiring pattern formed by a single wiring layer or two wiring layers. Accordingly, signal delay, which is often caused in a large scale semiconductor integrated circuit comprising a semiconductor device having an ultra-fine structure, is reduced. Also, more freedom is allowed in the design of the wiring pattern in such a large scale semiconductor integrated circuit.
In the conventional semiconductor device 10 shown in FIG. 1, however, there is the problem of contact resistance at the connecting portion between a conductive plug and the wiring pattern directly below the conductive plug. For instance, the wiring pattern 14b and the wiring pattern 18b are connected by a conductive plug that fills the contact hole 17b in the interlayer insulating film 17. The diameter of the contact hole 17b is substantially uniform and generally smaller than the width of the wiring pattern 14b, resulting in the contact resistance. The smaller the diameter of a contact hole, the greater the contact resistance. Accordingly, the contact resistance is a very serious problem in today""s semiconductor devices having an ultra-fine structure, which is so-called called submicron or sub-quarter-micron.
Furthermore, in the conventional semiconductor device 10 shown in FIG. 1, the diameter of the contact hole 17b is small. If the contact hole 17b deviates from a predetermined location in a photolithographic process, the contact area between the conductive plug and the wiring pattern 14b becomes even smaller, resulting in greater contact resistance. As the contact resistance increases, the time constant of the entire multilayer interconnection structure becomes greater. With the greater time constant, it is difficult to minimize signal delay.
A general object of the present invention is to provide semiconductor devices and semiconductor device production methods in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor device having a multilayer interconnection structure that reduces contact resistance between wiring layers, and a method of producing such a semiconductor device.
Another specific objects of the present invention is to provide a semiconductor device having a multilayer interconnection structure that prevents an increase of contact resistance even if a contact hole deviates from a predetermined location, and a method of producing such a semiconductor device.
The above objects of the present invention are achieved by a semiconductor device having a multilayer interconnection structure, comprising: a first-layer wiring pattern; an interlayer insulating film formed on the first-layer wiring pattern; a second-layer wiring pattern formed on the interlayer insulating film; and a conductive plug that is formed in the interlayer insulating film and connects the first-layer wiring pattern and the second-layer wiring pattern. The conductive plug comprises: a contact portion that contacts with the first-layer wiring pattern; and a connecting portion that extends from the contact portion toward the second-layer wiring pattern. The contact portion has a larger area than the connecting portion.
The above objects of the present invention are also achieved by a method of producing a semiconductor device that includes a first-layer wiring pattern, an interlayer insulating film formed on the first-layer wiring pattern, a second-layer wiring pattern formed on the interlayer insulating film, and a conductive plug formed in the interlayer insulating film so as to connect the first-layer wiring pattern and the second-layer wiring pattern, said method comprising the steps of:
forming a film on the first-layer wiring pattern, the film having a different etching rate from the interlayer insulating film;
forming the interlayer insulating film on the first-layer wiring pattern so as to cover the film;
forming a contact hole on the interlayer insulating film so as to expose the film;
removing the film by etching through the contact hole; and
forming the conductive plug in the contact hole so as to make electric contact with the first-layer wiring pattern.
By the above device or the method, an enlarged portion is formed at the lower end of a conductive plug in a multilayer interconnection structure, so that the contact resistance between the conductive plug and the wiring layer directly below the conductive plug can be minimized. Also, if a contact hole for forming the conductive plug deviates from a predetermined location, the enlarged portion ensures contact with the wiring layer.
The above and other objects and features of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.